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1 december 1996 hip4080 80v/2.5a peak, high frequency full bridge fet driver features ? drives n-channel fet full bridge including high side chop capability ? bootstrap supply max voltage to 95v dc ? drives 1000pf load at 1mhz in free air at 50 o c with rise and fall times of 10ns (typ) ? user-programmable dead time ? charge-pump and bootstrap maintain upper bias supplies ? dis (disable) pin pulls gates low ? input logic thresholds compatible with 5v to 15v logic levels ? very low power consumption applications ? medium/large voice coil motors ? full bridge power supplies ? class d audio power ampli?ers ? high performance motor controls ? noise cancellation systems ? battery powered vehicles ? peripherals ? u.p.s. description the hip4080 is a high frequency, medium voltage full bridge n-channel fet driver ic, available in 20 lead plastic soic and dip packages. the hip4080 includes an input comparator, used to facilitate the hysteresis and pwm modes of operation. its hen (high enable) lead can force current to freewheel in the bottom two external power mosfets, maintaining the upper power mosfets off. since it can switch at frequencies up to 1mhz, the hip4080 is well suited for driving voice coil motors, switching ampli?ers in class d high-frequency switching audio ampli?ers and power supplies. hip4080 can also drive medium voltage brush motors, and two hip4080s can be used to drive high performance step- per motors, since the short minimum on-time can provide ?ne micro-stepping capability. short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. the similar hip4081 ic allows independent control of all 4 fets in an full bridge con?guration. see also, application note an9324 for the hip4080. similar part, hip4080a, includes under voltage circuitry which doesnt require the circuitry shown in figure 30 of this data sheet. pinout hip4080 (pdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. hip4080ip -40 to 85 20 lead pdip e20.3 HIP4080IB -40 to 85 20 lead soic m20.3 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho file number 3178.10 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
2 application block diagram functional block diagram (1/2 hip4080) 80v gnd hip4080 gnd 12v load hen dis in+ in- bho bhs blo alo ahs aho charge pump v dd hen dis out in+ in _ hdel ldel v ss turn-on delay + - turn-on delay driver driver ahb aho ahs v cc alo als c bf to v dd (pin 16) c bs d bs high voltage bus 80v dc +12v dc level shift and latch 14 10 11 12 15 13 16 2 3 5 6 7 8 9 4 bias supply hip4080
3 typical application (hysteresis mode switching) 6v 80v 12v 12v dis in gnd 6v gnd + - 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho load hip4080
4 absolute maximum ratings thermal information supply voltage, v dd and v cc . . . . . . . . . . . . . . . . . . . -0.3v to 16v logic i/o voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ahs, bhs . . . . -6.0v (transient) to 80v (25 o c to 125 o c) voltage on ahs, bhs . . . . -6.0v (transient) to 70v (-55 o c to 125 o c voltage on als, bls . . . . . . . -2.0v (transient) to +2.0v (transient) voltage on ahb, bhbv ahs, bhs -0.3v to v ahs, bhs +16vvoltage on voltage on alo, blo . . . . . . . . . . . . v als, bls -0.3v to v cc +0.3v voltage on aho, bho . . . . . . v ahs, bhs -0.3v to v ahb, bhb +0.3v input current, hdel and ldel . . . . . . . . . . . . . . . . . . -5ma to 0ma phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns note: all voltages relative to pin 4, v ss , unless otherwise speci?ed. thermal resistance (typical, note 1) q ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum power dissipation at 85 o c soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470mw dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mw storage temperature range . . . . . . . . . . . . . . . . . . -65 o c to 150 o c operating max. junction temperature . . . . . . . . . . . . . . . . . 125 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. operating conditions supply voltage, v dd and v cc . . . . . . . . . . . . . . . . . . . +8v to +15v voltage on als, bls . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +1.0v voltage on ahb, bhb . . . . . . . . v ahs, bhs +5v to v ahs, bhs +15v input current, hdel and ldel. . . . . . . . . . . . . . . . -500 m a to -50 m a operating ambient temperature range . . . . . . . . . . .-40 o c to 85 o c electrical speci?cations v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed parameters symbol test conditions t j = 25 o c t j = - 40 o c to 125 o c units min typ max min max supply currents and charge pumps v dd quiescent current i dd in- = 2.5v, other inputs = 0v 8 10.5 13 7 14 ma v dd operating current i ddo outputs switching f = 500khz 9 11 14 8 15 ma v cc quiescent current i cc in- = 2.5v, other inputs = 0v, i alo = i blo = 0 - 25 80 - 100 m a v cc operating current i cco f = 500khz, no load 1 1.5 2.0 0.8 3 ma ahb, bhb quiescent current - qpump output current i ahb , i bhb in- = 2.5v, other inputs = 0v, i aho = i bho = 0, v dd = v cc = v ahb = v bhb = 10v -50 -30 -15 -60 -10 m a ahb, bhb operating current i ahbo , i bhbo f = 500khz, no load 0.5 0.9 1.3 0.4 1.7 ma ahs, bhs, ahb, bhb leakage current i hlk v ahs = v bhs = v ahb = v bhb = 95v - 0.02 1.0 - 10 m a ahb-ahs, bhb-bhs qpump output voltage v ahb - v ahs v bhb - v bhs i ahb = i ahb = 0, no load 11.5 12.6 14.0 10.5 14.5 v input comparator pins: in+, in-, out offset voltage v os over common mode voltage range -10 0 +10 -15 +15 mv input bias current i ib 0 0.5 2 0 4 m a input offset current i os -1 0 +1 -2 +2 m a input common mode voltage range cmvr 1 - v dd -1.5 1v dd -1.5 v voltage gain avol 10 25 - 10 - v/mv out high level output voltage v oh in+ > in-, i oh = -300 m av dd -0.4 --v dd - 0.5 -v out low level output voltage v ol in+ < in-, i ol = 300 m a - - 0.3 - 0.4 v high level output current i oh v out = 6v -9 -7 -4 -11 -2 ma low level output current i ol v out = 6v 8 10 12 5 14 ma input pins: dis low level input voltage v il full operating conditions - - 1.0 - 0.8 v high level input voltage v ih full operating conditions 2.5 - - 2.7 - v input voltage hysteresis - 35 - - - mv hip4080
5 low level input current i il v in = 0v, full operating conditions -130 -100 -75 -135 -65 m a high level input current i ih v in = 5v, full operating conditions -1 - +1 -10 +10 m a input pins: hen low level input voltage v il full operating conditions - - 1.0 - 0.8 v high level input voltage v ih full operating conditions 2.5 - - 2.7 - v input voltage hysteresis - 35 - - - mv low level input current i il v in = 0v, full operating conditions -260 -200 -150 -270 -130 m a high level input current i ih v in = 5v, full operating conditions -1 - +1 -10 +10 m a turn-on delay pins: ldel and hdel ldel, hdel voltage v hdel, vi hdel = i ldel = -100 m a 4.9 5.1 5.3 4.8 5.4 v gate driver output pins: alo, blo, aho, and bho low level output voltage v ol i out = 100ma .70 0.85 1.0 0.5 1.1 v high level output voltage v cc - v oh i out = -100ma 0.8 0.95 1.1 0.5 1.2 v peak pull-up current i o +v out = 0v 1.7 2.6 3.8 1.4 4.1 a peak pull-down current i o -v out = 12v 1.7 2.4 3.3 1.3 3.6 a electrical speci?cations v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed (continued) parameters symbol test conditions t j = 25 o c t j = - 40 o c to 125 o c units min typ max min max switching speci?cations v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 10k, c l = 1000pf, and t a = 25 o c, unless otherwise speci?ed parameters symbol test conditions t j = 25 o c t j = - 40 o c to 125 o c units min typ max min max lower turn-off propagation delay (in+/in- to alo/blo) t lphl - 40 70 - 90 ns upper turn-off propagation delay (in+/in- to aho/bho) t hphl - 50 80 - 110 ns lower turn-on propagation delay (in+/in- to alo/blo) t lplh r hdel = r ldel = 10k - 45 70 - 90 ns upper turn-on propagation delay (in+/in- to aho/bho) t hplh r hdel = r ldel = 10k - 70 110 - 140 ns rise time t r - 10 25 - 35 ns fall time t f - 10 25 - 35 ns turn-on input pulse width t pwin-on r hdel = r ldel = 10k 50 - - 50 - ns turn-off input pulse width t pwin-off r hdel = r ldel = 10k 40 - - 40 - ns disable turn-off propagation delay (dis - lower outputs) t dislow - 45 75 - 95 ns disable turn-off propagation delay (dis - upper outputs) t dishigh - 55 85 - 105 ns disable to lower turn-on propagation delay (dis - alo and blo) t dlplh - 35 70 - 90 ns refresh pulse width (alo and blo) t ref-pw 160 260 380 140 420 ns disable to upper enable (dis - aho and bho) t uen - 335 500 - 550 ns hen-aho, bho turn-off, propagation delay t hen-phl r hdel = r ldel = 10k - 35 70 - 90 ns hen-aho, bho turn-on, propagation delay t hen-plh r hdel = r ldel = 10k - 60 90 - 110 ns truth table input output in+ > in- hen dis alo aho blo bho x x10000 1 100110 0 101001 1 000010 0 001000 hip4080
6 pin descriptions pin number symbol description 1 bhb b high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of boot- strap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 30 m a out of this pin to maintain bootstrap supply. internal circuitry clamps the bootstrap supply to approximately 12.8v. 2 hen high-side enable input. logic level input that when low overrides in+/in- (pins 6 and 7) to put aho and bho drivers (pins 11 and 20) in low output state. when hen is high aho and bho are controlled by in+/in- inputs. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). an internal 100 m a pull-up to v dd will hold hen high, so no connection is required if high-side and low-side outputs are to be controlled by in+/in- inputs. 3 dis disable input. logic level input that when taken high sets all four outputs low. dis high overrides all other inputs. when dis is taken low the outputs are controlled by the other inputs. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). an internal 100 m a pull-up to v dd will hold dis high if this pin is not driven. 4v ss chip negative supply, generally will be ground. 5 out output of the input control comparator. this output can be used for feedback and hysteresis. 6 in+ non-inverting input of control comparator. if in+ is greater than in- (pin 7) then alo and bho are low level outputs and blo and aho are high level outputs. if in+ is less than in- then alo and bho are high level out- puts and blo and aho are low level outputs. dis (pin 3) high level will override in+/in- control for all outputs. hen (pin 2) low level will override in+/in- control of aho and bho. when switching in four quadrant mode, dead time in a half bridge leg is controlled by hdel and ldel (pins 8 and 9). 7 in- inverting input of control comparator. see in+ (pin 6) description. 8 hdel high-side turn-on delay. connect resistor from this pin to v ss to set timing current that de?nes the turn-on delay of both high-side drivers. the low-side drivers turn-off with no adjustable delay, so the hdel resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. hdel reference voltage is approximately 5.1v. 9 ldel low-side turn-on delay. connect resistor from this pin to v ss to set timing current that de?nes the turn-on delay of both low-side drivers. the high-side drivers turn-off with no adjustable delay, so the ldel resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. ldel reference voltage is approximately 5.1v. 10 ahb a high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of boot- strap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 30 m a out of this pin to maintain bootstrap supply. internal circuitry clamps the bootstrap supply to approximately 12.8v. 11 aho a high-side output. connect to gate of a high-side power mosfet. 12 ahs a high-side source connection. connect to source of a high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 13 alo a low-side output. connect to gate of a low-side power mosfet. 14 als a low-side source connection. connect to source of a low-side power mosfet. 15 v cc positive supply to gate drivers. must be same potential as v dd (pin 16). connect to anodes of two bootstrap diodes. 16 v dd positive supply to lower gate drivers. must be same potential as v cc (pin 15). de-couple this pin to v ss (pin 4). 17 bls b low-side source connection. connect to source of b low-side power mosfet. 18 blo b low-side output. connect to gate of b low-side power mosfet. 19 bhs b high-side source connection. connect to source of b high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 20 bho b high-side output. connect to gate of b high-side power mosfet. hip4080
7 timing diagrams figure 1. bi-state mode figure 2. high side chop mode figure 3. disable function hen = 1 alo aho blo t lphl t hplh t r (10% - 90%) t f (90% - 10%) t dt dis = 0 t hphl t lplh t dt in+ > in- bho hen alo aho blo t hen-plh t hen-phl in+ > in- bho dis = 0 hen = 1 aho blo dis t ref-pw t dlplh in+ > in- bho t dis t uen alo hip4080
8 typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed figure 4. quiescent i dd supply current vs v dd supply voltage figure 5. i ddo , no-load i dd supply current vs frequency (khz) figure 6. side a, b floating supply bias current vs frequency (load = 1000pf) figure 7. i cco , no-load i cc supply current vs frequency (khz) temperature figure 8. i ahb , i bhb , no-load floating supply bias current vs frequency figure 9. comparator input current i l vs temperature at v cm = 5v 8 10 12 14 2.0 4.0 6.0 8.0 10.0 12.0 14.0 i dd supply current (ma) v dd supply voltage (v) 13 12.5 12.0 11.5 11.0 10.5 10 200 400 600 800 1000 supply current (ma) switching frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 5.0 10.0 15.0 20.0 25.0 30.0 floating supply bias current (ma) switching frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0.0 1.0 2.0 3.0 4.0 5.0 i cc supply current (ma) switching frequency (khz) 75 o c 25 o c 125 o c -40 o c 0 o c 0 200 400 600 800 1000 -0.2 0.2 0.6 1.0 1.4 1.8 frequency (khz) floating supply bias current (ma) -40 -20 0 20 40 60 80 100 120 0.5 1.0 comparator input current ( m a) junction temperature ( o c) hip4080
9 figure 10. dis low level input current i il vs temperature figure 11. hen low level input current i il vs temperature figure 12. ahb - ahs, bhb - bhs no-load charge pump voltage vs temperature figure 13. upper disable turn-off propagation delay t dishigh vs temperature figure 14. disable to upper enable t uen propagation delay vs temperature figure 15. lower disable turn-off propagation delay t dislow vs temperature typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed (continued) -50 -25 0 25 50 75 100 125 -120 -110 -100 -90 low level input current ( m a) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 -230 -220 -210 -200 -190 -180 low level input current ( m a) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 10.0 11.0 12.0 13.0 14.0 15.0 no-load floating charge pump voltage junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 300 320 340 360 380 400 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) hip4080
10 figure 16. t ref-pw refresh pulse width vs temperature figure 17. disable to lower enable t dlplh propagation delay vs temperature figure 18. upper turn-off propagation delay t hphl vs temperature figure 19. upper turn-on propagation delay t hplh vs temperature figure 20. lower turn-off propagation delay t lphl vs temperature figure 21. lower turn-on propagation delay t lplh vs temperature typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed (continued) -40 -20 0 20 40 60 80 100 120 175 225 275 325 375 refresh pulse width (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 20 30 40 50 60 70 80 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 40.0 50.0 60.0 70.0 80.0 90.0 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 40.0 50.0 60.0 70.0 80.0 90.0 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 40.0 50.0 60.0 70.0 80.0 90.0 propagation delay (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 40.0 50.0 60.0 70.0 80.0 90.0 propagation delay (ns) junction temperature ( o c) hip4080
11 figure 22. gate drive fall time t f vs temperature figure 23. gate drive rise time t r vs temperature figure 24. v ldel , v hdel voltage vs temperature figure 25. high level output voltage, v cc - v oh vs bias supply and temperature at 100ma figure 26. low level output voltage v ol vs bias supply and temperature at 100ma figure 27. peak pulldown current i o vs bias supply voltage typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed (continued) -40 -20 0 20 40 60 80 100 120 8.5 9.5 10.5 11.5 12.5 13.5 gate drive fall time (ns) junction temperature ( o c) -40 -20 0 20 40 60 80 100 120 8.5 9.5 10.5 11.5 12.5 13.5 turn-on rise time (ns) junction temperature (c) -40 -20 0 20 40 60 80 100 120 4.0 4.5 5.0 5.5 6.0 hdel, ldel input voltage (v) junction temperature ( o c) 6 8 10 12 14 0 250 500 750 1000 1250 1500 v cc - v oh (mv) bias supply voltage (v) 75 o c 25 o c 125 o c -40 o c 0 o c 6 8 10 12 14 0 250 500 750 1000 1250 1500 v ol (mv) bias supply voltage (v) 75 o c 25 o c 125 o c -40 o c 0 o c 6 7 8 9 10 11 12 13 14 15 16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 gate drive sink current (a) v dd , v cc , v ahb , v bhb (v) hip4080
12 figure 28. peak pullup current i o+ vs supply voltage figure 29. low voltage bias current i dd and i cc (less quiescent component) vs frequency and gate load capacitance figure 30. high voltage level-shift current vs frequency and bus voltage figure 31. minimum dead-time vs del resistance typical performance curves v dd = v cc = v ahb = v bhb = 12v, v ss = v als = v bls = v ahs = v bhs = 0v, r hdel = r ldel = 100k, and t a = 25 o c, unless otherwise speci?ed (continued) 6 7 8 9 10 11 12 13 14 15 16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 gate drive sink current (a) v dd , v cc , v ahb , v bhb (v) 1 10 100 1000 2 5 20 50 500 200 0.1 1 10 100 500 50 5 0.5 200 20 2 0.2 low voltage bias current (ma) switching frequency (khz) 3,000 1,000 10,000 100 1 10 100 1000 2 5 20 50 200 500 1 10 100 1000 2 5 20 50 200 500 level-shift current ( m a) switching frequency (khz) 60v 40v 80v 20v 10 50 100 150 200 250 0 30 60 90 120 150 hdel/ldel resistance (k w ) dead-time (ns) hip4080
13 hip4080 power-up application information the hip4080 h-bridge driver ic requires external circuitry to assure reliable start-up conditions of the upper drivers. if not addressed in the application, the h-bridge power mos- fets may be exposed to shoot-through current, possibly leading to mosfet failure. following the instructions below will result in reliable start-up. the hip4080 does not have an input protocol like the hip4081 that keeps both lower power mosfets off other than through the dis pin. in+ and in- are inputs to a com- parator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming dis is low. however, keeping both lower mosfets off can be accom- plished by controlling the lower turn-on delay pin, ldel, while the chip is enabled, as shown in figure 32. pulling ldel to v dd will inde?nitely delay the lower turn-on delays through the input comparator and will keep the lower mos- fets off. with the lower mosfets off and the chip enabled, i.e. dis = low, in+ or in- can be switched through a full cycle, properly setting the upper driver outputs. once this is accomplished, ldel is released to its normal operating point. it is critical that in+/in- switch a full cycle while ldel is held high, to avoid shoot-through. this start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in figure 32. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 100k rdel rdel v dd 0.1 m f 2n3906 v dd enable v dd 56k 8.2v 56k 100k figure 32. v dd dis ldel =10ms t1 t2 8.3v to 9.1v (assuming 5% zener tolerance) 12v, final value 5.1v notes: 2. between t1 and t2 the in+ and in- inputs must cause the out pin to go through one complete cycle (transition order is not imp ortant). if the enable pin is low after the under-voltage circuit is satisfied, the enable pin will initiate the 10ms time delay during whi ch the in+ and in- pins must cycle at least once. 3. another product, hip4080a, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. figure 33. timing diagram for figure 32 hip4080
14 hip4080 1 2 3 1 3 1 3 6 5 1 2 3 2 1 12 13 1 3 10 11 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 l1 r21 q1 q3 q4 r22 l2 r23 c1 c3 jmpr1 r24 r30 r31 c2 r34 c4 cr2 cr1 q2 jmpr5 jmpr3 jmpr2 jmpr4 r33 c5 c6 cx cy c8 u1 cw cw + b+ in2 in1 bo out/bli in-/ahi com in+/ali +12v +12v bls ao hen/bhi als cd4069ub cd4069ub cd4069ub cd4069ub hip4080/81 section control logic power section driver section aho ahb ahs ldel alo hdel als in-/ahi v cc in+/ali v dd out/bli bls v ss blo dis bhs hen/bhi bho bhb r29 u2 u2 u2 u2 4 3 v dd cd4069ub u2 8 9 cd4069ub u2 v dd enable o 100k 0.1mfd i to dis 2n3906 56k 8.2v 56k o 2 2 2 notes: 4. circuit inside dashed area must be hardwired and is not included on the evaluation board. 5. device cd4069ub pin 7 = com, pin 14 = +12v. 6. components l1, l2, c1, c2, cx, cy, r30, r31, are not supplied. refer to application note for de- scription of input logic operation to determine jumper locations for jmpr1 - jmpr4. figure 34. hip4080 evaluation pc board schematic
15 hip4080 r22 1 q3 l1 c1 jmpr2 jmpr5 r31 r33 cr2 r23 r24 r27 r28 r26 1 q4 1 q2 jmpr3 u1 r21 gnd l2 c3 c2 c4 jmpr4 jmpr1 r30 cr1 u2 r34 bo ao r32 i o c8 r29 c7 c6 c5 cy cx 1 q1 com +12v b+ in1 in2 aho bho alo blo bls bls ldel hdel dis als als o + + hip4080/81 figure 35. hip4080 evaluation board silkscreen
16 supplemental information for hip4080 and hip4081 power-up application the hip4080 and hip4081 h-bridge driver ics require external circuitry to assure reliable start-up conditions of the upper drivers. if not addressed in the application, the h-bridge power mosfets may be exposed to shoot- through current, possibly leading to mosfet failure. follow- ing the instructions below will result in reliable start-up. hip4081 the hip4081 has four inputs, one for each output. outputs alo and blo are directly controlled by input ali and bli. by holding ali and bli low during start-up no shoot-through conditions can occur. to set the latches to the upper drivers such that the driver outputs, aho and bho, are off, the dis pin must be toggled from low to high after power is applied. this is accomplished with a simple resistor divider, as shown below in figure 36. as the v dd /v cc supply ramps from zero up, the dis voltage is below its input threshold of 1.7v due to the r1/r2 resistor divider. when v dd /v cc exceeds approxi- mately 9v to 10v, dis becomes greater than the input threshold and the chip disables all outputs. it is critical that ali and bli be held low prior to dis reaching its threshold level of 1.7v while v dd /v cc is ramping up, so that shoot through is avoided. after power is up the chip can be enabled by the enable signal which pulls the dis pin low. hip4080 the hip4080 does not have an input protocol like the hip4081 that keeps both lower power mosfets off other than through the dis pin. in+ and in- are inputs to a com- parator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming dis is low. however, keeping both lower mosfets off can be accom- plished by controlling the lower turn-on delay pin, ldel, while the chip is enabled, as shown in figure 37. pulling ldel to v dd will inde?nitely delay the lower turn-on delays through the input comparator and will keep the lower mos- fets off. with the lower mosfets off and the chip enabled, i.e., dis = low, in+ or in- can be switched through a full cycle, properly setting the upper driver outputs. once this is accomplished, ldel is released to its normal operating point. it is critical that in+/in- switch a full cycle while ldel is held high, to avoid shoot-through. this start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in figure 37. figure 36. figure 37. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 3.3k r2 enable r1 15k 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb bhi dis v ss bli ali hdel ahi ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 3.3k r2 r1 15k enable 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho 100k rdel rdel v dd 0.1 m f 2n3906 v dd enable v dd 56k 8.2v 56k 100k hip4080
17 timing diagrams note: 7. ali and/or bli may be high after t1, whereupon the enable pin may also be brought high. figure 38. note: 8. between t1 and t2 the in+ and in- inputs must cause the out pin to go through one complete cycle (transition order is not impor- tant). if the enable pin is low after the undervoltage circuit is satisfied, the enable pin will initiate the 10ms time delay during which the in+ and in- pins must cycle at least once. figure 39. v dd dis ali, bli 8.5v to 10.5v (assumes 5% resistors) 1.7v 12v, final value v dd dis ldel =10ms t1 t2 8.3v to 9.1v (assuming 5% zener tolerance) 12v, final value 5.1v hip4080
18 hip4080 notes: 1. symbols are de?ned in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m a m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 a 0 o 8 o 0 o 8 o - rev. 0 12/93 small outline plastic packages (soic)
19 hip4080 e20.3 (jedec ms-001-ad issue d) 20 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.55 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.980 1.060 24.89 26.9 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n20 209 rev. 0 12/93 notes: 1. controlling dimensions: inch. in case of con?ict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m b s e a -c- dual-in-line plastic packages (pdip) all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com

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